// Hello World

Arnuv Batra

Hardware Engineer & Entrepreneur

ECE student at UPenn building computers from silicon to systems: FPGA RTL, ASIC design, and embedded hardware. Currently at SpaceX writing FPGA RTL for Starship.

Interests: RTL· FPGA· ASIC· Embedded Systems· Computer Architecture

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01 / About

BS + MS in Electrical & Computer Engineering at the University of Pennsylvania. I work on digital circuits, FPGA/ASIC design, and computer architecture.
Outside of school, I like to play & watch sports, read, and listen to music.

02 / Experience

  1. Silicon Engineering Intern

    SpaceX

    May 2026 — Aug 2026

    • Building high-reliability FPGA RTL for mission-critical DSP & radio comms on Starship

  2. Digital Electronics Intern

    Lutron Electronics

    May 2025 — Aug 2025

    • Worked on cutom new shading product w/ digital circuit design & simulation

  3. Teaching Assistant — ESE 1900/1110 Silicon Garage

    University of Pennsylvania

    Jan 2025 — Present

    • Lead labs on semiconductors & electronics

  4. Summer Researcher

    Beaver Works at MIT

    June 2024 — August 2024

    • Led RTL of custom AQI-monitoring ASIC; earned Best Project Award among 100+ projects

  5. Co-founder / CEO

    Fall Vision LLC

    July 2020 — June 2024

    • Patent-pending IoT fall-detection hardware w/ C & Python pipelines; won County's Young Entrepreneur Award
03 / Projects
Featured 2026 · RTL

Pipelined RISC-V CPU with Cache Integration

Architected a 5-stage pipelined RISC-V CPU with custom branch prediction, hazard detection, and bypassing logic — achieving a course-best clock frequency of 44 MHz. Integrated a custom AXI4-Lite cache, custom 8-stage Divider Module, and validated the SoC on Lattice FPGA Board with Candy Crush demo.

44 MHz
Frequency (course best)
5
Pipeline stages
AXI4-Lite
Bus protocol
SystemVerilog RISC-V AXI4-Lite FPGA

16-bit Asynchronous FIFO

RTL

Built an asynchronous FIFO in Verilog & ModelSim; implemented clock-domain crossing with multi-flop synchronizers. FPGA benchmarking in progress.

Verilog ModelSim FPGA

PennOS — Kernel & OS

Software

UNIX-like guest OS designed around custom priority scheduler, FAT file system, and interactive user shell. Built in C on Linux.

C Scheduler FAT FS Shell

Spike Sure Rim Detection

Hardware

3D-printed chassis & custom PCB with ARM processor and microphone for detecting rim points in Spikeball via FFT analysis; beta tested at 3+ local tournaments.

ARM PCB Design Signal Processing

Magnetically Levitating Flywheel Generator

Hardware

Senior capstone: custom circuit and PCB, machined aluminum and 3D-printed parts to generate electricity in remote areas using a magnetically levitating flywheel.

PCB Design SolidWorks RTL

SmartTable for Competitive Foosball

Hardware

Designed a microcontroller circuit & custom IoT setup for foosball score tracking with AI-based lifetime and in-game analytics. Best Overall Project among 30+ projects.

PCB Microcontrollers IoT

Birthday Circuit Curriculum

Hardware

Modernized a 1990s Wellon PLC-based course to an Arduino-simulated FPGA system — freshmen now display their birthday on a 7-segment with boolean logic.

FPGA Boolean Logic Curriculum
04 / Skills

Hardware

  • Verilog / SystemVerilog
  • FPGA
  • ASIC / RTL
  • PCB Design
  • Computer Architecture
  • Embedded Systems

Software

  • C / C++
  • Python
  • CUDA
  • OS Development
  • AI / ML
  • Linux / Bash
05 / Contact

Always open to chatting about RTL, FPGAs, hardware, or new opportunities.

avbatra@upenn.edu LinkedIn GitHub